<br><br>Job Description<br> Synopsys is seeking a motivated and innovative digital verification engineer intern to join the team. As an intern, you will contribute to the verification of current and next-generation SERDES products by writing constrained-random System Verilog test benches using UVM and VMM, defining and tracking verification test plans, and debugging RTL and gate-level simulation failures. <br><br>Responsibilities <br>- Writing constrained-random System Verilog test benches using UVM and VMM <br>- Writing new cover groups and examining functional, assertions, and code coverage <br>- Defining and tracking verification test plans <br>- Debugging RTL and gate-level simulation failures <br><br>Requirements <br>- Bachelor’s or Master’s Degree in ECE/EEE <br>- Experience with scripting languages such as Perl, Python, Unix shell <br><br>About Synopsys Synopsys’ Silicon IP business focuses on integrating more capabilities into an SoC, helping customers meet unique performance, power, and size requirements while reducing risk and time to market. Synopsys is at the forefront of innovations in self-driving cars, AI, cloud computing, 5G, and the Internet of Things. They are committed to diversity and inclusion, considering all applicants without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. <br><br>Location: INDIA - Hyderabad <br><br>Job Requisition ID: 51397BR <br><br>Position Type: Intern
